Ask Slashdot: Getting Apps To Use Phones' Full Power?

First time accepted submitter MurukeshM writes "I have a 16 GB Nexus 4. I rarely manage to push the RAM usage above 1 GB (not counting cached processes). Yet I find it increasingly annoying when apps do stuff to save on RAM usage, such as having a browser reload a tab if I havent used it for a long time, instead of keeping it in memory or have an ebook reader load from storage instead of keeping the entire eBook in RAM. I know there are plenty of phones with far less memory, but when most of the RAM is unutilized, with more and more phones and tablets having 1GB+ RAM, isn't it time that apps check on available RAM and use optimizations accordingly? And it isn't only about RAM. Android by default only downloads one thing at a time, whether it be an app from Play Store or a file from a site. When connected to WiFi or 3G/LTE, there's no reason why multiple simultaneous downloads shouldn't be used. How do Slashdot readers with high-end phones get the most out of their device? Are there custom ROMs which act more sensibly?"

That phone has 2GB of RAM

[Anonymous Coward]

The 16GB Nexus 4 doesn't have 16GB of RAM. It has 2GB. Your post reads like you think it has 16GB of RAM.

Comment removed

[account_deleted]

Comment removed based on user account deletion

Re:Read up on ARM

[TheRaven64]

This is a platform that was not designed to have a scheduler carving up resources

Uh, what? The ARM architecture was designed for Acorn's line of 32-bit desktop computers, which shipped with a multitasking OS from the start. Now, it wasn't preemptively multitasking, but the only difference between cooperative multitasking and preemptive from a hardware perspective is that you need (relatively) cheap timer interrupts to enable preemptive multitasking, and ARM has always had this.

The cost of context switching boils down to a small number of things:

• The cost of delivering the timer interrupt (interrupts on ARM are cheap and have a small number of aliased registers to play with so the code in the interrupt handler can be simple)
• The size of the register set that needs to be saved (ARM is 15 32-bit GPRs, which can be saved and loaded in a single multi-cycle instruction, only x86 has a smaller register set)
• The cost of TLB flushes and refills required during the switch (ARM has a tagged TLB, so you only need to invalidate any TLB entries when you recycle an ASID)

In summary, the orifice that you are talking out of is not your mouth.